还是写下来，用的少记不住
1.verilog +：
reg [31:0] dword;
reg [7:0] byte0;
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;
assign byte0 = dword[0 +: 8]; // Same as dword[7:0]
assign byte1 = dword[8 +: 8]; // Same as dword[15:8]
assign byte2 = dword[16 +: 8]; // Same as dword[23:16]
assign byte3 = dword[24 +: 8]; // Same as dword[31:24]
2.clog2
//$clog2(x)是将x取以2为底的对数并且向上取整
temp = $clog2(1); //0
temp = $clog2(2); //1temp = $clog2(3); //2temp = $clog2(4); //2temp = $clog2(5); //3temp = $clog2(6); //3